Manufacturers consistently try to reduce the size of products, such as cellular telephones, computers, and digital cameras in order to meet consumer demands. All of these electronic products require integrated circuit (IC) assemblies. Thus, it is important to continue to reduce the size of these IC assemblies, without sacrificing performance, in order to reduce the overall product size.
IC assemblies may include a plurality of interconnected IC chips, which also are referred to as dies. One or more dies are stacked in a particular location on a substrate surface. The substrate location is referred to as a die attach area. Typically, an array of such die stacks is formed on a substrate, and the die stacks are separated into individual packages along saw lines to form the end-product. For convenience, this specification typically refers to plural dies; however, all statements apply equally to a semiconductor package having only one die.
A die stack is referred to as a single stack if there is a single die stacked in a particular location on the substrate. If plural dies are stacked on top of each other in a particular location on the substrate, the stack is referred to as a multiple stack. A semiconductor package can comprise one die stack (whether a single or multiple stack). Alternatively, a semiconductor package can comprise more than one die stack, and some or all of the stacks can be single stacks, while some or all of the stacks can be multiple stacks.
Dies typically are physically coupled to the substrate via an adhesive layer. Each die also is effectively electrically connected to the substrate. This electrical connection can be created using thin conductive wires, such as gold wires or aluminum wires. Alternatively, dies can be electrically connected to the substrate via small solder balls, using, for example, the flip chip method. These and other methods are well known in the industry. The area where dies are electrically coupled to the substrate can be referred to as the conductive element bonding area or, in the case where wire bonds are present, as the wire bonding area. Dies are first electrically connected to the substrate as desired, and then the die substrate assembly is encapsulated by a protective molding compound, usually comprising a polymer, ceramic, epoxy, or combinations thereof. Encapsulation protects the dies and electrical connections by creating a moisture barrier to prevent physical, chemical and/or electrical damage to the components.
The substrate, die stack, and encapsulating material combine to form a “package.” A cross sectional drawing of a representative prior art package 100 is illustrated in FIG. 1. Illustrated package 100 comprises a substrate 102 and four stacked dies 104, 106, 108, 110 attached to substrate 102 or to another die, via die adhesive layers 103, 105, 107, and 109. Package 100 further comprises solder balls 112 along one surface of substrate 102. Solder balls 112 provide input and output access to dies 104, 106, 108, and 110 once package 100 is connected to a circuit board for use in an electronic product. Semiconductor package 100 has been encapsulated with molding compound 114. Plural conductive bond wires 118 electrically couple each die 104, 106, 108, and 110 to substrate 102.
Numerous different packages 100 are known and used in the art. Some common examples include the polymer ball grid array package, such as the plastic ball grid array (PBGA) package, and the fine ball grid array (FBGA) package. The package also can include a heat spreader, which covers the dies and conductive wires, in order to improve heat transfer, such as during the encapsulation process. Although semiconductor packages, such as package 100, are widely used, however problems still exist with the encapsulation process.
Still with reference to FIG. 1, during the encapsulation process, a mold is placed over dies 104, 106, 108, and 110 and substrate 102, leaving a small gap 116 between the top of molding compound 114 and the top of die 110. Gap 116 is herein referred to as the encapsulant gap 116, and also represents the distance between the top of die 110 and the package surface once encapsulation is complete. Once the mold is in place, a molding compound 114 is injected into the mold, and flows over dies 104, 106, 108, and 110 inside the mold. Molding compound 114 typically is injected at a temperature high enough that molding compound 114 is in a liquid or semi-liquid state, and therefore flows over dies 104, 106, 108, and 110 and substrate 102. Molding compound 114 then cools and hardens to protect substrate 102, dies 104, 106, 108, and 110, and electrical connections, such as bond wires 118.
The encapsulant gap has a significant impact on the molding process. As mentioned above, manufacturers need to keep package size as small as possible, even though dies often are stacked to create IC assemblies to use space most efficiently. As dies are stacked, the encapsulant gap decreases. But as the encapsulant gap decreases, molding compound flow is affected and can become uneven. As a result, various defects in the finished product, such as internal and external voids, wire sweeping, and wire shorts, can occur. Internal and external voids are essentially areas where air has been trapped by molding compound (where air fails to escape), resulting in holes or voids in the package. External voids can subject the device to moisture damage, which can ruin the device. Internal voids may expand if exposed to heat and eventually cause the package layers to separate. In semiconductor packages containing bond wires, another potential problem during the molding process is wire sweeping, where molding compound deforms or breaks the conductive wires, or causes two different bonding wires to contact, creating electrical shorts in the device.
Devices do exist ostensibly designed to reduce air pocket formation. For example, see U.S. Pat. No. 6,969,640 to Dimaano et al., which discloses an “air pocket resistant semiconductor package system.” Dimaano discloses using individual heat spreaders placed around each die. Each heat spreader has an encapsulant guide and an air vent, to prevent air pocket formation.
Additionally, U.S. Pat. No. 6,750,533 to Wang et al., discloses a “substrate with dam bar structure for smooth flow of encapsulating resin.” Wang's FIG. 1 shows a plan view of a semiconductor package comprising dam bar 56 on substrate 5. “The dam bar 56 formed on the substrate 5, as shown in FIG. 1, is preferably provided with a first gate 560 directed toward the molding gate 55, a second gate 561, and a third gate 562 opposed to the second gate 561, wherein the second and third gates 561, 562 are vertically arranged in position with respect to the molding gate 55; this allows the dam bar 56 to be divided into four sections by means of the first, second and third gates 560, 561, 562.” Column 4, line 66 through column 5, line 6. “The first gate 560 is sized smaller than the second and third gates 561, 562 respectively.” Column 5, lines 7-8. “The geometry, shape and height of the dam bar 56 are critical factors for affecting mold flow of the encapsulating compound.” The molding compound is “impeded by the dam bar 56, and diverts to flow through the second and third gates 561, 562.” Column 5, lines 20-21.
“As shown in [Wang] FIG. 3A, a simple dam bar 56a is formed with a gate 560a directed toward the molding gate 55, and has found to be ineffective for impeding mold flow of the molding compound.” Column 5, lines 51-54. “A dam bar 56b of [Wang] FIG. 3B is similar in structure to the dam bar 56a of [Wang] FIG. 3A, with the difference in that the dam bar 56b is dimensioned with increased length, and a gate 560b of the dam bar 56b is sized smaller than the gate 560a of the dam bar 56a. It has been found that, such a dam bar 56b would reduce a flowing speed of the molding compound.” Column 5, lines 55-60. Thus, the properly sized gate is identified as a critical factor by Wang.
Wang FIG. 4 shows a plan view of a semiconductor package comprising dam bar 65 positioned on substrate 6, with flow of the molding compound indicated by the arrow. However, as positioned in Wang FIG. 4, dam bar 65 does not appear capable of controlling the flow of molding compound over each of the chips 63. For example, dam bar 65 is not positioned to effectively control molding compound flow over chip 63.
Moreover, Wang discloses only curvilinear or rectangular dam bars geometry, as illustrated in Wang FIG. 1, 3A, 3B, and 4. The height of the dam bar disclosed in Wang must be at least 75 % of the height of the mold cavity. The dam bar impedes molding compound flow by forcing the molding compound through the gates of the dam bar. Column 6, lines 18-30. As such, the dam bars disclosed in Wang are not well-suited for use in an arrayed semiconductor package with saw lines.
The prior art does not address all potential problems associated with molding compound flow and the encapsulation process. For example, known devices and methods do not effectively control molding compound flow over all areas of the semiconductor package.